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Hello everyone , this is my block digram , my final implemented design gives me setup violation for 16 end points from fifo to cic compiler,how to debug this.
Size: a a a
2019 April 22
AS
have you tried adding a register between FIFO and the first CIC?
AS
or as I see, it is a clock domain crossing logic (CDC)?
AS
is that FIFO asynchronous?
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Yes fifo is asynchronous. I don't know how to build cdc logic
AS
well first of all you need to learn about the concept of cross-domain logic and how to pass data through different clock domains
AS
This is a good paper for this:
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Yes ,i tried two flip flop logic for slow clock domain to fast clock domain data transfer.. but is giving me same no of failing end points.
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I tried two then three flipflop logic but result is same.
AS
failing endpoints is another topic
AS
I am not sure that your design is correct there in the first place
AS
but if and when it is correct
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Ok
AS
Then in the tools like Vivado it is often needed to write additional constraints for CDC crossings, like in async FIFOs
AS
something like this:
AS
set_false_path \
-from [get_clocks psync_i] \
-to [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path \
-from [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]] \
-to [get_clocks psync_i]
A
Okay.. i will try this
A
Thanks for the help
AS
these constraints are not your solution by the way, but a hint for you what to do